NSAP-2 - NOT Simple As Possible (name is still a work in progress...)
NSAP-2 - NOT Simple As Possible (name is still a work in progress...)
I decided to try my hand at a new design from scratch, but following the spirit of the SAP series of CPUs.
My design goals are to end up with a more powerful and useful CPU, with a defined separation between the CPU and the other components in a computer.
Elements of this design are borrowed from many different CPU architectures of the time, including the 8008, 6502, and z80 processors.
The CPU will remain primarily on breadboards, with the 8-bit data bus and 16-bit address bus connected by a ribbon cable to a custom backplane PCB.
Memory will be connected by the backplane, and will provide a boot-loader in ROM, paged RAM, and bank switching.
Hardware I/O will be in a separate address space from memory, and segmented akin to the "expansion slots" found in most 8-bit computers of the time.
The initial primary human interface will be a Serial UART port with basic input/output routines, along with a "monitor" program in ROM.
This will allow memory contents to be updated, and programs run, by a keyboard and text display on an attached serial terminal.
16-bit address bus, 64K addressable memory
Separate 16-bit hardware bus, 256 devices with 256 addressable I/O space
8-bit data bus and op-codes
Logical separation of CPU internal and external components
Front "Nostalgia" Panel
Program Loader and ROM Monitor
Hardware "expansion" bus
UART Serial port for terminal IO