Control Logic

I swapped the two AT28C16 chips (16k bits / 2k bytes) with a number of AT28C256 chips (256k bits / 32k bytes) that I had on hand.These chips have an additional 4 address lines, for a total of 15 instead of 11.

The address lines have 4 bits for the sub-step (up from 3), 8 bits for the instruction (up from 4), 2 bits for the "chip select" (up from 1), removes the two flags completely, and still has one address line free.

This allows for 4 eeprom chips and 4x8=32 data lines for control signals. It can also have 16 sub-steps instead of 8.

To handle conditional jumps, and make microcode generation simpler, each jump instruction now has a control signal (data pin) assigned to its op-code, just as the unconditional "JMP" instruction does, and the truth condition is now checked in hardware.

For example, just as the "JMP" op-code sets the "J" control signal, the "JZ" op-code sets a "JZ" control signal. This signal is AND'ed with the current "ZF" flag state, and the result of the AND triggers a jump in the PC if true.