Combinational Logic
Combinational Logic
The SAP-1 design uses ROM chips to provide the combinational logic for both the output modules character generation and the microcode instructions. Specifically, Ben's implementation uses 16k-bit / 2048 byte EEPROMs in DIP packaging for breadboard use.
For the address line inputs, 8 bits are used for the binary value to display, 2 bits to select one of the four digits, and 1 bit to select normal vs twos compliment conversion.
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Two ROM chips are used in parallel to provide 16 data line outputs to manage the control signals through out the CPU.
The address line inputs use 4 bits for the op-code instruction, 3 bits to encode up to 8 sub-steps per instruction, 2 bits for flag registers, and 1 bit as a form of "chip select". This allows for a single binary image containing both ROM chip contents, selected based on breadboard wiring.
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These two ROM chips provide the logic gate functionality as shown in this image.
It contains 148 AND gates, 110 NOT gates, and 19 OR gates, using 7 inputs and 16 outputs.